He shares his best tips, tricks, and techniques that will help you to utilize the flexible and inexpensive PSoC to its greatest potential, with a minimum of heartaches and late nights. You will add brains and capable signal conditioning to a design with one chip, giving you extreme flexibility for a relatively low price. Embedded design expert Robert Ashby will guide you through the entire PSoC world, providing thorough coverage The PSoC blocks usage is divided into digital, analog continuous blocks, and analog switched capacitor blocks. There is also a section that shows application programming interface API memory usage.
This section is subdivided into Flash usage and RAM usage. For example, an 8-bit serial receiver block is shown as needing one digital block. However, in my project, this module will require one of the digital communication blocks which limits its placement into four of the available blocks. These characteristics may change from one family of parts to another. The sample code is given in both assembly and in C for your convenience. These registers can be accessed in two ways when you are writing code. Resource Meter The right side of the user module selection view displays the resource meter.
The Total column indicates what resources are available based on the part selected for your project. There are also some code compilation optimizations that can be performed that will help to save on usage of ROM. The meter is intended as a reference only. It is given as a quick visual reference to the operation and design of the currently selected module.
A double-click on a module from the left will add that module to the project. Alternatively, you can right-click on the module and choose Select to add it to your project. You can rename the module with a name of your choosing. Even though you might be able to keep all the inner workings of your project straight, this is useful particularly for the next person who has to work with your project. Renaming the module is accomplished by selecting the instance that you want to rename and then right-clicking on that instance.
One of the selections of the Context menu will be Rename. Select the Rename option and you can type in a new name for this module. If you have selected an improper name, PSoC Designer will stop you as soon as you press enter. Refer to Figure Figure Interconnect View The global resources are found in the top left of the interconnect view.
You will notice a drop-down box next to the name of each global resource. The drop-down box will list all possible settings for that resource. By choosing a particular setting for the global resource, you are telling PSoC Designer what value to load in the associated control register during boot. Following are quick descriptions of global resources.
Refer to Appendix A for more information on global resources. This clock is based off SysClk. You can choose one of several divisions of this clock if you want a slower operation frequency. Before you start thinking that faster is always better, take into account that a slower processor uses less power and is more noise immune.
Make sure that you take your power supply into account, as the slower speeds allow you to operate the processor over a larger voltage range without risking bad fetches from Flash memory. If you choose External, then the micro tries to drive a crystal at those pins. This gives you a higher accuracy on your internal 24 MHz. Sleep Timer The sleep timer resource allows you to adjust the frequency of the sleep timer.
A slower sleep period saves power, but also means that you will have a slower response waking up from the lower power state. VC2 24V2 is derived from VC1 and has the potential to divide by interger values up to VC3 only present on newer parts has four sources: VC3 has the potential to divide by VC3 also can be an interrupt to the processor on terminal count.
It allows you to select a source for your SysClk. It can be the internal 24 MHz oscillator or an external source. Analog Power This allows you to turn your switched cap blocks on and off. It also allows you to set a power level for the reference voltage. Ref Mux The ref mux can seem a little confusing. This allows your analog-to-digital converters to work from GND to Vcc and your gain stages to work as you would probably expect. The ref mux sets the reference levels that are used in the analog blocks of the PSoC.
There are also some options to use external pins to set these levels. Op-Amp Bias The op-amp bias is left low for most projects. A high setting gives you a faster slew rate, but less voltage swing. Choices are low or high. High power can mean a more stable voltage. The switch mode pump is used with a simple circuit to pump up a low voltage source to a voltage level where the PSoC can operate.
LVD is the level at which a low voltage detection circuit will trip. The SMP is the level at which the switch mode pump starts to transition to pump the voltage back up to a safe level. It is designed to slow down processor operation at lower voltages to help with accurate operation. Supply Voltage The supply voltage option allows you to select between the two expected operating voltages. This option is used to determine oscillator trim values for the internal oscillator. Watchdog Enable The watchdog enable option is used in boot.
I have only touched on the basics of the global resources in this chapter. User Module Parameters The user module parameters appear directly under the global resources. The values available for this module will appear as a drop-down box or can be adjusted with buttons to the right of the value. This gives you a visual method to see the available values for that particular parameter. The name is not currently used in code generation.
Options are disabled, rising edge, falling edge, or a change from last read. A right-click on the module in this section allows you to place or unplace the module, call up the data sheet, block diagram, adjust the color, or rename the module. A click of the mouse while holding the Ctrl key will zoom in on the area where the mouse is located. Holding the Alt key will dragging with the mouse allows you to pan around different areas of the screen. Certain parameters of the digital and analog blocks can be set by clicking the respective graphical location of the module placed in that block.
You are not able to set parameters of empty blocks in this manner. Left clicking on a multiplexer, analog output buffer or analog clock will allow you to choose the options available for that particular resource. Improvements to PSoC Designer when they created 4.sushioffer.archidelivery.ru/js/fizika/2586.html
Designer's guide to the Cypress PSoC, Volume 10 - PDF Free Download
You should be able to see visually a connection from a digital block outputting a PWM signal go from the digital block through the lines on the screen to the icon with the name of the desired pin. This is one area where you just need to spend some time clicking around on the screen to discover what is possible. Application Editor The application editor is a multiple document text editor with advanced editor features. It is used to modify the code associated with your project.
The project explorer can be toggled on and off by selecting Project from the View menu. This pane can be toggled on and off by selecting Output from the View menu. Cypress has done a good job with the editor functions. They allow you, through editor options, to enable an output tab in your project view. The bottom toolbar gives you the ability to call up data sheets from any of their modules. There is an icon on the toolbars that looks like a wrench crossed with a hammer. This is the editor toolbox. The emulator pod has adapters, called feet, that allow adaptation to the different sizes of packages.
This method was designed for through-hole systems. The ICE system recently changed from a plain white unimaginative box to a new cube design that looks like it is a descendant of an iMac computer peripheral, complete with impressive blue LEDs. The connection to the emulator pods of the older ICE system is with an 8-pin RJ45 cable very similar to a standard network cable. This system can still be used with the new ICE cube via an adapter. They are designed to be soldered directly onto your project board. Since the feet system was a little fragile and tended to come apart, I shied away from using it.
Some engineers actually glued the parts together to keep them from coming apart. The debugger system of the PSoC has been useful in my experience, but also a little buggy. You may stop a couple of instructions later. The events capabilities of the Cypress debugger are very impressive however. Events allow you set up logical conditions which when met will break operation, turn the trace on or off, or set an external trigger. It is a very powerful tool. PSoC Designer is constantly being revamped for improvements, so annoyances are short-lived. This means that projects done in older versions will need to be upgraded when moving onto a newer version.
This has caused a couple of hiccups in my projects in the past. The PSoC family has a lot of capability despite its shortcomings. This chapter is not intended to discourage you from using the PSoC part, but will show you some of the limitations that you might encounter while doing your project. The linear output range extends to approximately 0. The continuous time blocks are designed to work centered around AGND rather than towards either rail.
In our example we have Vcc set at 5 volts. As your input voltage rises above 2. This exceeds the limitation of 0. If you have an analog input signal that is close to the rail limitations, you should try to get that signal closer to AGND. I did some design on a motor controller project that required me to read the current going through the motor. Current would be measured by measuring the voltage across a 0. The expected range of the motor current that I would need to interpret would be from 0 to 30 amps with 0. You can quickly see that I would be dealing with small voltages on the current sense pin to interpret my current readings.
One method that Cypress 68 Limitations of the PSoC suggested to me to get this signal into a more usable range involved a simple addition of two resistors as shown in Figure When Signal In is at 0 volts, I would expect to see around 0. If the Signal In voltage were at 3 volts, then I would expect to see around 3. This is shown in Equation The newer versions of PSoC greatly improved this limitation.
Those parts will have an input range of Vss to Vcc. The analog output buffer pins also fall under an output limitation. They only guarantee the output to go from 0. You should also note that reducing the load on the output of these buffers would help them to output voltages closer to Vcc and GND. I would recommend that you have some kind of external buffer if you plan on driving much current. Another characteristic of the analog output buffers is that they will draw more current as they get closer to the positive and negative rails. The comparator is going to output either GND or Vcc. Fortunately, the output was a debugging option on my project and I was able to make a simple code change to shut off the output.
If you need to get the output of a comparator to an external pin, allot appropriate digital sources in order to feed the comparator bus out a digital output rather than using the analog output buffers. A board change at that point would have been costly and time consuming. You could think of it as another voltage added to your input.
With a gain of 1, this only equates to 1. The newer PSoC parts have a much smaller input offset. The typical offset of the 27xxx part is only around 3. One of my earlier projects with the PSoC involved conversion of an analog signal that was measured in small fractions of a mV. The signal that I was interpreting was referenced to ground, so we added a voltage divider circuit to our incoming signal to pull it away from the ground reference.
Refer to the rail limitation section earlier in this chapter. Due to the small voltages and larger gains that I was applying to the input voltage, I needed to have some way to reduce or eliminate the input offset of the gain stages. By storing the input offset number that was present at the output of the gain stages at that point, I was able to subtract that offset number from the readings of the analog-to-digital converter during operation.
This allowed me to determine the reading of the analog signal without the added error of an unknown offset voltage. Gain Deviation My project to measure a small analog voltage mentioned in this section ran into another snag that had to be dealt with. This is the gain deviation of the continuous analog blocks. The gain deviation is affected by two factors: Gain Deviation As you can see by the graph, you could experience a large variance in the actual gain value if you set up a large gain at low power. The easiest way to eliminate most of this error is to use high power to blocks that have a large gain.
In fact, my advice is to set all analog blocks up as high power when you start your design. If a power issue arises after your design is working, then look to see where you can conserve power. Because the power setting of the block is simply a value in a register, you can easily set the block to a lower power setting or turn the block off during times of inactivity or in low-power modes when gain accuracy may not be as important.
The data sheet for the 26xxx part shows a variance from the gain that can be expected by mentioning gain variances for a few of the levels for high power only. It refers to the chart for a more complete picture. Please note that the gain tends to be lower than nominal at high gains and higher than nominal at gains less than 1. The newer parts that use the improved analog show a great improvement with gain variation. Unfortunately, they have chosen not to include a graphical representation of how this gain can vary like they have in the 26xxx data sheet.
They simply give typical values for various gains. The values from the 27xxx data sheet are as follows. Gain Setting 48 24 16 4 1 Typical Deviation 4. The deviation of gain at a gain of 16 is now expected to be just 1. Note that the numbers listed in the table of the 26xxx parts show a grimmer outlook on gain deviation than the graph does. If the error were to follow a more standard deviation bell curve type of error similar to a statistics problem, then the problem might be addressed by daisy chaining several small gains together.
This would tend to even out the distribution and give a smaller overall error on average. However, the gain deviation tends to be in one direction. This would negate that effect. Looking at the percentages of gain error, I would even suppose that it might be slightly worse to take that approach. In my project, gain error was a concern, so I looked at two possible solutions. The more complex approach is to try to calculate the deviation amount.
This is accomplished by taking a reading of a stable voltage at a gain of 1. After getting that reading at a gain of 1, change the gain the higher value that you expect to run at and then take a reading again. Compare that reading to the initial gain reading taking into account the differences in gain to calculate the expected gain error.
There are some limitations in this of course, particularly if you need a lot of accuracy in your reading, but it will help you explore options to determine the true gain deviation of that part. Switched Cap Blocks The switched cap blocks are built around the concept that you can switch a capacitor in a way for it to look like resistor. Variations on how you switch the capacitor will let you change the resistive value. This means that you need to synchronize with the signal as you pass it from block to block. Fortunately, Cypress has made this extremely simple and handles most of the work for you.
If your design requires adjusting on when it samples the signal, you only need to be worried about two times where the sampling will occur. This is denoted in PSoC Designer as clock phase. The two settings for clock phase are normal and swap. You will see this setting on modules such as the 8-bit delta-sigma analog-to-digital converter ADC.
I have been able to leave this setting at default normal for all of my projects with no problem. The clocking source for each column of analog is selectable. Signals can reach a level where they are too fast for the clock sources available and they will be distorted at the output. The selected clock for a column of analog blocks applies to all the blocks within that column. The SAR operates by stalling the processor to make its calculations on what level the analog signal is at.
Designer's Guide to the Cypress PSoC (Embedded Technology) by Robert Ashby PDF
Since the amount of time that the processor stalls is directly proportional to the clock rate of the analog clock, I found that my chip would spend an inordinate amount of time whenever I tried to get a new sample. The sad twist of fate was that the sample was being taken from within a timed interrupt and the amount of time to process a sample exceeded the period of time before a new interrupt came pending.
This is due to both the architecture of the different switched cap blocks and to the arrangement of the switched cap blocks. The 27xxx and all other newer parts have type C and type D switched cap blocks. There are equal numbers of each type of blocks; the arrangement of the two types of blocks within the interconnect view is similar to the layout of a checkerboard with its black and red squares. This checkerboard arrangement allows the user to get the most variety in block arrangement within a particular part providing columns with the A type block on top and columns with it on the bottom.
It also allows you to choose a column that has an AB arrangement when looking from left to right, or a BA arrangement. By trying to give you all possible arrangement types, you end up limiting the number of any given particular arrangement. I was not able to set up all my outputs as desired because of the layout of the blocks on the chip. I only discovered my mistake after actually placing 76 Limitations of the PSoC the blocks. Only then did the light go on, which left me returning to the design group with the disappointing news, which caused unnecessary redesign work.
It only takes a few minutes to place the blocks that you think you will need for a project. I would suggest that you take those few minutes immediately after you have enough information to know which blocks you will need to place. This way you will not be surprised towards the end of the game by a roadblock that inconveniences everyone. Signal Routing One improvement to the newer PSoC parts that I believe was well needed is the ability to route an analog signal directly into a switched cap block. Some possibilities can be seen by trying all possible placements of an 8-bit delta-sigma ADC block in a 27xxx part.
You can see that there is a new input option that appears on the leftmost two switched cap blocks and on the rightmost two switched cap blocks. The blocks on the left allow you to choose port2 and the blocks on the right allow you to choose port2. I imagine that the inputs are available with blocks on the extremities because these blocks have less interconnects routed through them than the center blocks do.
Bits 1 and 2 of port 2 are used to connect to the A mux of the switched cap block. This is why they appear for the ADC. The DCAxx blocks are used for communication, in addition to being able to perform normal timing, PWM and other functions. These blocks have some enhancements. In addition, Cypress has enhanced the interconnectability around the digital blocks, which allows you to achieve more complex projects. The best way to prevent panic in your design is to set out all the blocks needed for a project and connect the blocks before committing to a design.
The older Designer versions were a bit more cryptic on exactly what was going on. You can learn a lot by simply clicking around in the interconnect view of Device Editor to explore how things are connected. These communication blocks comprise half of the digital blocks available on most parts.
Therefore, if you are going to use a CY part, you will only be able to use four blocks for communications function. This allows you to have two full UARTs. Likewise with a part, you are only able to have two full UARTs. You can insert an 8-bit serial receiver block and simply use the one block to receive, thereby freeing up an extra digital block in your project.
This means that these blocks can only be connected to the global buses 4—7. Therefore, you are only able to connect these pins out the high nibbles of any particular port. Only one of the transmitters may connect to the global bus bit 7, not both. You will need to move one of the transmitters to a different bit, such as port1, to be able to route your signal to the output pin.
You can, however, use the same bit for one input and one output. When Cypress created the 27xxx series, and with other newer parts, they rearranged how the blocks are organized. Rather than have one row of normal timing blocks and one row of digital communication blocks, they interspersed the communication blocks.
You have two timing blocks and two communication blocks on each row of digital blocks. Timing Inputs Digital input blocks are able to access timing from 16 different sources. The need to plan out timing can come early on in the game. You should lay out your blocks and resources as quickly as possible to make sure that you have everything covered. Some of the resources that you think may be there could end up not being there.
Several clock sources are available to the digital blocks as listed in the global resources. In addition to the global clock sources you can also use the output signals of other blocks as the clock source. This could easily be needed, especially if you want to get to a lower baud rate. Since the UART modules require two digital blocks for each instance, you will have consumed all four digital communication blocks.
It is the one other digital block clock source that jumps the gap, going from the lower nibble to the higher nibble. You can also use global output 4 to get signals from the higher nibble to the lower nibble. In this situation then, you have one timer in a lower nibble digital block that is outputting a needed clock frequency for one UART and one timer in DBA03 outputting the frequency needed for the other UART. That only leaves two blocks left if you implement the timing in an 8-bit timer. This situation is a good example of how the resources of the PSoC micro can easily be expended. This might come into play as you plan out your project.
However, the Zilog Z8 Encore! This situation is yet another good example of why you should lay out all your blocks and interconnects as quickly as possible when planning a project. The newer 27xxx series and other newer PSoC parts change the structure of the digital blocks by putting communication blocks in both rows of digital blocks. You can place timers in the blocks immediately to the left of the communication blocks and use the previous block option for both UARTs.
It also gives you the opportunity to use two bit timers to time your UART blocks if desired. Then there is a broadcast line that originates from DBA The DBA03 broadcast and these other options are available to all digital blocks. The remaining options depend on what block you are in. There is the interconnect that connects to the output of the block immediately to its left as viewed in PSoC Designer.
It will be referred to as the previous digital PSoC block clock select in the data sheet. These options are described graphically in Figure This allows another path for you to get a timing signal from one row of logic to another as was shown in the previous section. By using the newer parts, your options have changed somewhat. I think the best way to illustrate this would be to show the clocking options of an 8-bit timer placed in block DBA01 on a 26xxx part and an 8-bit timer placed in block DBB01 on a 27xxx part.
It lists a row broadcast rather than a broadcast from a particular block. This system will allow you to get signals transferred from either row of digital blocks to the other regardless of which block you want the signal source to come from. In addition, you can use the row broadcast signals independently from each other to allow you to interconnect signals from nonconsecutive blocks on both rows without wasting the global connections. The next option for the previous block is identical. Both rows of digital blocks are now able to go to both nibbles of all output pins.
These are acronyms for global input odd and global input even. Port 0 is an even port, 83 Chapter 4 Port 1 is an odd port and so on. More details on how to use these interconnects and other new features are discussed in Chapter 5 — Improvements of the PSoC and Chapter 7 — Interconnects. They have been able to increase functionality and still keep the price of their parts competitive with traditional microcontrollers. This chapter will discuss in a little more detail some of the improvements in the newer families of Cypress Semiconductor Corporation products.
There are yet some more parts that are in the design stage that will be available by the time this book is printed. I will not, however, include those parts in this edition. They held true to their word. Cypress Semiconductor Corporation 85 Chapter 5 knows that real world engineers cringe at words like compromise and additional time so they have worked feverishly on improving their analog subsystems. They have done an excellent job with their second generation of parts. I look forward to even newer designs on the horizon which will add function and capability beyond what we have now.
Cypress kept up numerous errata and application notes to document and provide work arounds for the various situations. Since all circuits have some component of resistance, capacitance, and inductance, you need to ensure that the circuit is built around tight enough tolerances to be certain that the internal signals of the microcontroller will reach an adequate voltage level in the time needed in order to work consistently. As you can imagine, however, trying to decipher the situation where an instruction straddles a page boundary is quite daunting. It was a painful circumstance to tell everyone that you would need to stay at the lower 12 MHz operating speed.
Cypress therefore worked on incorporating a check for the potential problem into the next version of PSoC Designer. A simple checkbox would tell PSoC Designer to warn the user when this type of problem could exist. This method worked for 86 Improvements of the PSoC most situations. The newer parts were redesigned in this area to make the 24 MHz alignment shift unnecessary. The part can run at 24 MHz in all situations. However, you can go anywhere below that.
Using this method, if a more accurate clock is available, then you can use that clock source instead of relying on the internal oscillator. You also can feed in some more desired frequencies. For anyone who has done serial RS communications, you know that trying to get a baud rate of , , , etc. You will have a slight error in your actual baud rate. This is acceptable in many situations, but in the situations that need to have a more accurate system, you buy crystals that work at a frequency that is a multiple of your desired baud rate. Now you have the opportunity to input that frequency in the PSoC microcontroller so that the entire system will be able to generate several of these baud rates with complete accuracy.
It differs from VC1 and VC2 in that it has a larger range and can be used as an interrupt source. There are certainly other functions that VC3 can serve. First of all VC3 has four different potential clock sources: This gives it the chance to output an additional signal of a different frequency in the same range area as VC1 and VC2, or you can get a signal that is much lower than these two by having VC2 as a source. By using all three VC clocks together, you can produce a frequency of less than Hz with the internal oscillator and without using any digital blocks.
VC3 also will provide an interrupt at its terminal count. Since I like to have projects that have events happen in a timely manner at regular intervals, I use the VC3 clock as a interrupt source for my fastest desired interval and then divide that interval down further with software. This works very well and saves the use of the digital block that I used in the past for this purpose.
Appendix B — Project Walkthrough illustrates an example project of this type. This was not possible on the older parts without using a global bus line or the DBA03 broadcast signal. Another improvement with the digital blocks in the new PSoC families is the addition of the synchronization parameter. The new PSoC families allow you to input an external signal for SysClk, so synchronization with the internal 24 MHz clock might not have any practical effect. Therefore the option is given to you to synchronize to SysClk so that you will be synchronized correctly regardless of the source of SysClk.
Each allowed synchronization follows simple guidelines on when to select that particular option. This also applies if the clock source for your block is the output of another digital block that uses a clock derived from the SysClk. Synchronization is then left up to the user. This is the same frequency as SysClk and you should use SysClk.
Previously, there were 16 global bus lines. Eight lines are used to input signals and eight lines are used to output signals. It was possible to bring a signal in on one global bus line and connect it to multiple blocks. You could also use a global output line that would pass the output of one digital block to an external pin and even use this output bus as the input for another digital block. Each global bus would connect to the corresponding bit of any particular port. Changing hardware is exactly the type of thing that you want to avoid, so Cypress found some ways to improve these interconnects.
There is an advantage to this in that you are able to interconnect two digital blocks and still leave all the global buses free for other uses. Connecting between the global bus array is now through an input multiplexer or an output de-multiplexer. The input multiplexers are attached to the red input rows that are positioned above the digital blocks in the interconnect view. Clicking on one of these input rows will show the possible connections of the interconnect line to global input signals to the left of the digital blocks. The output de-multiplexers are connected to the blue output rows that are positioned below the digital blocks in the interconnect view.
Likewise, clicking on the output row will display the possible connections to the global output signals. This method allows a particular row to connect with twice as many locations as the old parts. In addition, the newer interconnects allow you to have two global input signals on the same bit from two different ports. Please refer to Chapter 7 — Interconnects to learn more about interconnects. There is also a separate broadcast signal on the bottom row of digital blocks that acts in the same way.
The two broadcast signals can be linked together to allow the broadcast signal from one row to be used by digital blocks on the other row.
LUTs in Key Locations Digital outputs and comparator buses have logic look up tables that allow you to add some simple logic to their signals, which would previously have required a digital block. I had a project that required the output of a UART module to be inverted. In addition, the extra digital block had to reside on the same row and thereby cost me a digital communication block rather than a digital basic block. This extra register is used with some more complex drive logic to give the additional open drain modes including active low or active high states , slow strong drive, or high impedance analog.
The open drain modes are useful for implementing communication buses such as I2C or multiple master situations where you want to prevent damage to components without the addition of external circuitry to add the open drain method. You will still need to add the external resistor to assert the inactive state. The slow strong drive removes the high frequencies generated by faster changing signals. These two situations tend to make an effective antenna that could be disruptive to other parts of your design or nearby electronics. This reduces the current draw in your project.
The data sheet refers to it as the zero power state. This is the default state at reset. The current data sheet does not show the actual input impedance improvement from between the High-Z and High-Z analog settings. Continuous Time Analog Blocks The continuous time analog blocks have been improved in their structure. The input voltage swing is listed to be from Vss to Vdd.
I have taken this number from the PGA data sheet. The general data sheet for the parts lists different numbers. I suggest that you adhere to the numbers that accompany the user modules. I believe that the numbers in these situations take into account other factors that may affect the capabilities of the components used by the module. Chapter 2 — Structure of the PSoC also mentioned two other important improvements: In addition to the increased voltage ranges, the continuous time blocks allow for two more gain settings. These gain settings will allow you to amplify your incoming signal by 24 or If you are our guide to this chip you would think that it would contain something at least as good as what you can find on the online application notes at Cypress.
I will not buy anything from this author again. Would not even use it as a reference because the information is uncomplete. The online data sheets are sufficient for that. One person found this helpful 2 people found this helpful. It is written clearly and in the same easy going style that Mr Ashby used so successfully in his articles on chipcenter. To his credit, Mr Ashby does not reproduce data sheets nor does he toe the Cypress line. He takes a practical approach that proves a great deal of experience in the embedded field. As a result you get general microcomputer knowledge along with PSoC specifics.
This book is not a reference of all things PSoC, nor does it pretend to be. It is the ideal text to get you up to speed on the PSoC even if you have previous microcomputer experience. The book directly addresses the idiosyncrasies of the PSoC and has a great summary of the PSoC modules that allows for a quick review and comparison to facilitate the choice of which module to use.
There is also a great example on the use of multiple configurations. Mr Ashby also addresses simple level shifting of analog input signals. The book is further enhanced by details on the optimization settings of the PSoC Designer and has a chapter dedicated memory management that covers RAM and Flash settings, both from the project perspective including personal utilities and how to implement them through directives to the assembler.
The appendix that covers global resources contains good reference material on meaning of the different settings within the Global Resources window in PSOC Designer and there is also a wealth of information that is covered in the appendix on a "Project Walkthrough". There is a chapter on PSoC Express. You will not find any description of the emulator or programmer in this book.
Perhaps the author felt that it was too project specific to be able to cover in sufficient depth, or that he would be duplicating existing Cypress documentation. It is a pity because I feel that Mr Ashby's style would have been very helpful in understanding the more adavnceds features of the emulator. Unfortunately this edition of the book will likely have a short half-life, given the rate of change of PSoC Designer and the PSoC chips. All in all, the book is a worthwhile addition to the library of anyone designing with the PSoC. This book is a skeleton summary of the basic concepts.
The author does not go into depth on any particular design-related topic. IMHO, the title is misleading. As another reviewer mentioned, all information in this book can be found on the Cypress website and in the PSoC Designer help index as well as user module datasheets. There is almost no tips, tricks or examples to help a designer such as myself that understands the basics. I'd say the only thing that this book could be good for is to help make a quick decision whether to use a PSoC for a particular project or not.